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rev. 1.3 aug. 2005 256mb, 512mb unbuffered dimms ddr2 sdram ddr2 unbuffered sdram module 240pin unbuffered module based on 256mb f-die 64/72-bit non-ecc/ecc * samsung electronics reserves the right to change products or specification without notice. information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granti ng any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about sams ung products, contact your nearest samsung office. 2. samsung products are not intended for use in life suppor t, critical care, medical, safety equipment, or similar applications where product failure coul dresult in loss of life or personal or physical harm, or any military or defense application, or any governm ental procurement to which specia l terms or provisions may apply.
rev. 1.3 aug. 2005 256mb, 512mb unbuffered dimms ddr2 sdram ddr2 unbuffered dimm ordering information note: ?z? of part number(11th digit) stand for lead-free products. note: ?3? of part number(12th digit) stand for dummy pad pcb products. part number density organization component composition number of rank height x64 non ecc m378t3253fg(z)3-ce6/d5/cc 256mb 32mx64 32mx8(k4t56083qf)*8 1 30mm m378t3253fg(z)0-ce6/d5/cc 256mb 32mx64 32mx8(k4t56083qf)*8 1 30mm m378t6453fg(z)3-ce6/d5/cc 512mb 64mx64 32mx8(k4t56083qf)*16 2 30mm m378t6453fg(z)0-ce6/d5/cc 512mb 64mx64 32mx8(k4t56083qf)*16 2 30mm x72 ecc m391t3253fg(z)3-ce6/d5/cc 256mb 32mx72 32mx8(k4t56083qf)*9 1 30mm m391t3253fg(z)0-ce6/d5/cc 256mb 32mx72 32mx8(k4t56083qf)*9 1 30mm m391t6453fg(z)3-ce6/d5/cc 512mb 64mx72 32mx8(k4t56083qf)*18 2 30mm m391t6453fg(z)0-ce6/d5/cc 512mb 64mx72 32mx8(k4t56083qf)*18 2 30mm features ? performance range ? jedec standard 1.8v 0.1v power supply ?v ddq = 1.8v 0.1v ? 200 mhz f ck for 400mb/sec/pin, 267mhz f ck for 533mb/sec/pin, 333mhz f ck for 667mb/sec/pin ? 4 banks ? posted cas ? programmable cas latency: 3, 4, 5 ? programmable additive latency: 0, 1 , 2 , 3 and 4 ? write latency(wl) = read latency(rl) -1 ? burst length: 4 , 8(in terleave/nibble sequential) ? programmable sequential / interleave burst mode ? bi-directional differential data-strobe (s ingle-ended data-strobe is an optional feature) ? off-chip driver(ocd) impedance adjustment ? on die termination ? average refresh period 7.8us at lower than a t case 85 c, 3.9us at 85 c < t case < 95 c - support high temperature self-refresh rate enable feature ? package: 60ball fbga - 32mx8 ? all of lead-free products are compliant for rohs note: for detailed ddr2 sdram operation, please refer to samsung?s device operation & timing diagram. e6(ddr2-667) d5(ddr2-533) cc(ddr2-400) unit speed@cl3 400 400 400 mbps speed@cl4 533 533 400 mbps speed@cl5 667 - -mbps cl-trcd-trp 5-5-5 4-4-4 3-3-3 ck address configuration organization row address column address bank address auto precharge 32mx8(256mb) based module a0-a12 a0-a9 ba0-ba1 a10
rev. 1.3 aug. 2005 256mb, 512mb unbuffered dimms ddr2 sdram x64 dimm pin configurations (front side/back side) nc = no connect, rfu = reserved for future use 1. pin173 pin174 are reserved for 2gb/4gb comp. base unbuffered dimm. 2. the test pin is reserved for bus analysis tools and is not connected on standard memory module products (dimms.) pin front pin back pin front pin back pin front pin back pin front pin back 1 v ref 121 v ss 31 dq19 151 v ss 61 a4 181 v ddq 91 v ss 211 dm5 2 v ss 122 dq4 32 v ss 152 dq28 62 v ddq 182 a3 92 dqs 5212 nc 3 dq0 123 dq5 33 dq24 153 dq29 63 a2 183 a1 93 dqs5 213 v ss 4 dq1 124 v ss 34 dq25 154 v ss 64 v dd 184 v dd 94 v ss 214 dq46 5 v ss 125 dm0 35 v ss 155 dm3 key 95 dq42 215 dq47 6dqs 0 126 nc 36 dqs 3 156 nc 65 v ss 185 ck0 96 dq43 216 v ss 7 dqs0 127 v ss 37 dqs3 157 v ss 66 v ss 186 ck 097 v ss 217 dq52 8 v ss 128 dq6 38 v ss 158 dq30 67 v dd 187 v dd 98 dq48 218 dq53 9 dq2 129 dq7 39 dq26 159 dq31 68 nc 188 a0 99 dq49 219 v ss 10 dq3 130 v ss 40 dq27 160 v ss 69 v dd 189 v dd 100 v ss 220 ck2 11 v ss 131 dq12 41 v ss 161 nc 70 a10/ap 190 ba1 101 sa2 221 ck 2 12 dq8 132 dq13 42 nc 162 nc 71 ba0 191 v ddq 102 nc, test 2 222 v ss 13 dq9 133 v ss 43 nc 163 v ss 72 v ddq 192 ras 103 v ss 223 dm6 14 v ss 134 dm1 44 v ss 164 nc 73 we 193 s 0 104 dqs 6224 nc 15 dqs 1 135 nc 45 nc 165 nc 74 cas 194 v ddq 105 dqs6 225 v ss 16 dqs1 136 v ss 46 nc 166 v ss 75 v ddq 195 odt0 106 v ss 226 dq54 17 v ss 137 ck1 47 v ss 167 nc 76 s 1 196 nc 107 dq50 227 dq55 18 nc 138 ck 1 48 nc 168 nc 77 odt1 197 v dd 108 dq51 228 v ss 19 nc 139 v ss 49 nc 169 v ss 78 v ddq 198 v ss 109 v ss 229 dq60 20 v ss 140 dq14 50 v ss 170 v ddq 79 v ss 199 dq36 110 dq56 230 dq61 21 dq10 141 dq15 51 v ddq 171 cke1 80 dq32 200 dq37 111 dq57 231 v ss 22 dq11 142 v ss 52 cke0 172 v dd 81 dq33 201 v ss 112 v ss 232 dm7 23 v ss 143 dq20 53 v dd 173 nc 82 v ss 202 dm4 113 dqs 7233 nc 24 dq16 144 dq21 54 nc 174 nc 83 dqs 4 203 nc 114 dqs7 234 v ss 25 dq17 145 v ss 55 nc 175 v ddq 84 dqs4 204 v ss 115 v ss 235 dq62 26 v ss 146 dm2 56 v ddq 176 a12 85 v ss 205 dq38 116 dq58 236 dq63 27 dqs 2 147 nc 57 a11 177 a9 86 dq34 206 dq39 117 dq59 237 v ss 28 dqs2 148 v ss 58 a7 178 v dd 87 dq35 207 v ss 118 v ss 238 vddspd 29 v ss 149 dq22 59 v dd 179 a8 88 v ss 208 dq44 119 sda 239 sa0 30 dq18 150 dq23 60 a5 180 a6 89 dq40 209 dq45 120 scl 240 sa1 90 dq41 210 v ss
rev. 1.3 aug. 2005 256mb, 512mb unbuffered dimms ddr2 sdram x72 dimm pin configurations (front side/back side) nc = no connect, rfu = reserved for future use 1. pin173 pin174 are reserved for 2gb/4gb comp. base unbuffered dimm. 2. the test pin is reserved for bus analysis tools and is not connected on standard memory module products (dimms.) pin front pin back pin front pin back pin front pin back pin front pin back 1 v ref 121 v ss 31 dq19 151 v ss 61 a4 181 v ddq 91 v ss 211 dm5 2 v ss 122 dq4 32 v ss 152 dq28 62 v ddq 182 a3 92 dqs 5 212 nc 3 dq0 123 dq5 33 dq24 153 dq29 63 a2 183 a1 93 dqs5 213 v ss 4dq1124 v ss 34 dq25 154 v ss 64 v dd 184 v dd 94 v ss 214 dq46 5 v ss 125 dm0 35 v ss 155 dm3 key 95 dq42 215 dq47 6dqs 0 126 nc 36 dqs 3156 nc 65 v ss 185 ck0 96 dq43 216 v ss 7dqs0127 v ss 37 dqs3 157 v ss 66 v ss 186 ck 097 v ss 217 dq52 8 v ss 128 dq6 38 v ss 158 dq30 67 v dd 187 v dd 98 dq48 218 dq53 9 dq2 129 dq7 39 dq26 159 dq31 68 nc 188 a0 99 dq49 219 v ss 10 dq3 130 v ss 40 dq27 160 v ss 69 v dd 189 v dd 100 v ss 220 ck2 11 v ss 131 dq12 41 v ss 161 cb4 70 a10/ap 190 ba1 101 sa2 221 ck 2 12 dq8 132 dq13 42 cb0 162 cb5 71 ba0 191 v ddq 102 nc, test 2 222 v ss 13 dq9 133 v ss 43 cb1 163 v ss 72 v ddq 192 ras 103 v ss 223 dm6 14 v ss 134 dm1 44 v ss 164 dm8 73 we 193 s 0104dqs 6 224 nc 15 dqs 1 135 nc 45 dqs 8165 nc 74 cas 194 v ddq 105 dqs6 225 v ss 16 dqs1 136 v ss 46 dqs8 166 v ss 75 v ddq 195 odt0 106 v ss 226 dq54 17 v ss 137 ck1 47 v ss 167 cb6 76 s 1 196 nc 107 dq50 227 dq55 18 nc 138 ck 1 48 cb2 168 cb7 77 odt1 197 v dd 108dq51228 v ss 19 nc 139 v ss 49 cb3 169 v ss 78 v ddq 198 v ss 109 v ss 229 dq60 20 v ss 140 dq14 50 v ss 170 v ddq 79 v ss 199 dq36 110 dq56 230 dq61 21 dq10 141 dq15 51 v ddq 171 cke1 80 dq32 200 dq37 111 dq57 231 v ss 22 dq11 142 v ss 52 cke0 172 v dd 81 dq33 201 v ss 112 v ss 232 dm7 23 v ss 143 dq20 53 v dd 173 nc 82 v ss 202 dm4 113 dqs 7 233 nc 24 dq16 144 dq21 54 nc 174 nc 83 dqs 4 203 nc 114 dqs7 234 v ss 25 dq17 145 v ss 55 nc 175 v ddq 84 dqs4 204 v ss 115 v ss 235 dq62 26 v ss 146 dm2 56 v ddq 176 a12 85 v ss 205 dq38 116 dq58 236 dq63 27 dqs 2 147 nc 57 a11 177 a9 86 dq34 206 dq39 117 dq59 237 v ss 28 dqs2 148 v ss 58 a7 178 v dd 87 dq35 207 v ss 118 v ss 238 vddspd 29 v ss 149 dq22 59 v dd 179 a8 88 v ss 208 dq44 119 sda 239 sa0 30 dq18 150 dq23 60 a5 180 a6 89 dq40 209 dq45 120 scl 240 sa1 90 dq41 210 v ss pin description * the vdd and vddq pins are tied to the single power-plane on pcb. pin name description pin name description a0-a12 ddr2 sdram address bus ck0, ck1, ck2 ddr2 sdram clocks (positive line of differential pair) ba0, ba1 ddr2 sdram bank select ck 0, ck 1, ck 2 ddr2 sdram clocks (negative line of differential pair) ras ddr2 sdram row address strobe scl i 2 c serial bus clock for eeprom cas ddr2 sdram column address strobe sda i 2 c serial bus data line for eeprom we ddr2 sdram wirte enable sa0-sa2 i 2 c serial address select for eeprom s 0, s 1 dimm rank select lines v dd * ddr2 sdram core power supply cke0,cke1 ddr2 sdram clock enable lines v ddq * ddr2 sdram i/o driver power supply odt0, odt1 on-die termination control lines v ref ddr2 sdram i/o reference supply dq0 - dq63 dimm memory data bus v ss power supply return (ground) cb0 - cb7 dimm ecc check bits v dd spd serial eeprom positive power supply dqs0 - dqs8 ddr2 sdram data strobes nc spare pins(no connect) dm(0-8) ddr2 sdram data masks reset not used on udimm dqs 0-dqs 8 ddr2 sdram differential data strobes test used by memory bus analysis tools (unused on memory dimms)
rev. 1.3 aug. 2005 256mb, 512mb unbuffered dimms ddr2 sdram input/output functional description symbol type function ck0-ck2 ck 0-ck 2 input ck and ck are differential clock inputs. all the sdram addr/cntl inputs are sampled on the crossing of positive edge of ck and negative edge of ck . output (read) data is reference to the crossing of ck and ck (both directions of crossing) cke0-cke1 input activates the sdram ck signal when high and deactivates the ck signal when low. by deactivating the clocks, cke low initiates the powe down mode, or the self-refresh mode s 0-s 1 input enables the associated sdram command decoder when low and disables the command decoder when high. when the command decoder is disbled, new command are ignored but previous operations continue. this signal provides for exter- nal rank selection on systems with multiple ranks ras , cas , we input ras , cas , and we ( along with cs) define the command being entered. odt0-odt1 input when high, termination resistance is enabled for all dq, dq and dm pins, assuming the function is enabled in the extended mode register set (emrs). v ref supply reference voltage for sstl 18 inputs. v ddq supply power supply for the ddr ii sdram output buffers to provide improved noise immunity. for all current ddr2 unbuffered dimm designs, vddq shares the same power plane as vdd pins. ba0-ba1 input selects which sdram bank of four is activated. a0-a13 input during a bank activate command cycle, address input defines the row address (ra0-ra13) during a read or write command cycle, address input defines the colum address, in addition to the column address, ap is used to invoke autoprecharge operation at the end of the burst read or write cycle. if ap is high, autoprecharge is selected and ba0, ba1 defines the bank to be precharged. if ap is low, autoprecharge is disbled. during a precharge command cycle, ap is used in conjunction with ba0, ba1 to control which bank(s) to precharge. if ap is high, all banks will be precharged regardless of the state of ba0, ba1. if ap is low, ba0, ba1are used to define which bank to pre- charge. dq0-dq63 cb0-cb7 in/out data and check bit input/output pins. dm0-dm8 input dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. v dd ,v ss supply power and ground for ddr2 sdram input buffers, and core logic. vdd and vddq pins are tied to v dd /v ddq planes on these modules. dqs0-dqs8 dqs 0-dqs 8 in/out data strobe for input and output data. for rawcards using x16 orginized drams dq0-7 connect to the ldqs pin of the drams and dq8-17 connect to the udqs pin of the dram sa0-sa2 input these signals and tied at the system planar to either v ss or v dd to configure the serial spd eerpom address range. sda in/out this bidirectional pin is used to transfer data into or out of the spd eeprom. a resistor must be connected from the sda bus line to vdd to act as a pullup on the system board. scl input this signal is used to clock data into and out of the spd eeprom. a resistor may be connected from the scl bus time to vdd to act as a pullup onthe system board. v dd spd supply power supply for spd eeprom. this supply is separate from the v dd /v ddq power plane. eeprom supply is operable from 1.7v to 3.6v.
rev. 1.3 aug. 2005 256mb, 512mb unbuffered dimms ddr2 sdram s 0 dqs 0 dqs0 dm0 dm cs dqs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 dqs 1 dqs1 dm1 dm cs dqs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 dqs 2 dqs 2 dm2 dm cs dqs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 dqs 3 dqs3 dm3 dm nu/ cs dqs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 dqs 4 dqs4 dm4 dm cs dqs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 dqs 5 dqs5 dm5 dm cs dqs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d5 dqs 6 dqs6 dm6 dm cs dqs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d6 dqs 7 dqs7 dm7 dm cs dqs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d7 notes : 1. dq,dm, dqs/dqs resistors : 22 ohms 5%. 2. bax, ax, ras , cas , we resistors : 5.1 ohms 5%. functional block diagram: 256mb, 32mx64 module (populated as 1 rank of x8 ddr2 sdrams) a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp *wire per clock loading table/wiring diagrams * clock wiring clock input ddr2 sdrams *ck0/ ck0 *ck1/ ck1 *ck2/ ck2 2 ddr2 sdrams 3 ddr2 sdrams 3 ddr2 sdrams v ss d0 - d7 v dd /v ddq d0 - d7 d0 - d7 vref v ddspd serial pd a0 - a12 a0-a12 : ddr2 sdrams d0 - d7 ras ras : ddr2 sdrams d0 - d7 cas cas : ddr2 sdrams d0 - d7 we we : ddr2 sdrams d0 - d7 cke0 cke : ddr2 sdrams d0 - d7 ba0 - ba1 ba0-ba1 : ddr2 sdrams d0 - d7 odt0 odt : ddr2 sdrams d0 - d7 m378t3253fg(z)3 / m378t3253fg(z)0
rev. 1.3 aug. 2005 256mb, 512mb unbuffered dimms ddr2 sdram s 0 dqs 0 dqs0 dm0 dm cs dqs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 dqs 1 dqs1 dm1 dm cs dqs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 dqs 2 dqs 2 dm2 dm cs dqs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 dqs 3 dqs3 dm3 dm cs dqs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 dqs 4 dqs4 dm4 dm cs dqs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 dqs 5 dqs5 dm5 dm cs dqs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d5 dqs 6 dqs6 dm6 dm cs dqs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d6 dqs 7 dqs7 dm7 dm cs dqs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d7 notes : 1. dq,dm, dqs/dqs resistors : 22 ohms 5%. 2. bax, ax, ras , cas , we resistors : 5.1 ohms 5%. functional block diagram: 256mb, 32mx72 ecc module (populated as 1 rank of x8 ddr2 sdrams) a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp *wire per clock loading table/wiring diagrams * clock wiring clock input ddr2 sdrams *ck0/ ck0 *ck1/ ck1 *ck2/ ck2 3 ddr2 sdrams 3 ddr2 sdrams 3 ddr2 sdrams v ss d0 - d8 v dd /v ddq d0 - d8 d0 - d8 vref v ddspd serial pd dqs 8 dqs8 dm8 dm cs dqs dqs cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d8 a0 - a12 a0-a12 : ddr2 sdrams d0 - d8 ras ras : ddr2 sdrams d0 - d8 cas cas : ddr2 sdrams d0 - d8 we we : ddr2 sdrams d0 - d8 cke0 cke : ddr2 sdrams d0 - d8 ba0 - ba1 ba0-ba1 : ddr2 sdrams d0 - d8 odt0 odt : ddr2 sdrams d0 - d8 m391t3253fg(z)3 / m391t3253fg(z)0
rev. 1.3 aug. 2005 256mb, 512mb unbuffered dimms ddr2 sdram s 0 dqs 0 dqs0 dm0 dm cs dqs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 dqs 1 dqs1 dm1 dm cs dqs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 dqs 2 dqs 2 dm2 dm cs dqs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 dqs 3 dqs3 dm3 dm cs dqs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 dqs 4 dqs4 dm4 dm cs dqs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 dqs 5 dqs5 dm5 dm cs dqs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d5 dqs 6 dqs6 dm6 dm cs dqs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d6 dqs 7 dqs7 dm7 dm cs dqs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d7 notes : 1. dq,dm, dqs/dqs resistors : 22 ohms 5%. 2. bax, ax, ras , cas , we resistors : 3 ohms 5%. functional block diagram: 512b, 64mx64 module (populated as 2 ranks of x8 ddr2 sdrams) a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp *wire per clock loading table/wiring diagrams * clock wiring clock input ddr2 sdrams *ck0/ ck0 *ck1/ ck1 *ck2/ ck2 4 ddr2 sdrams 6 ddr2 sdrams 6 ddr2 sdrams v ss d0 - d15 v dd /v ddq d0 - d15 d0 - d15 vref v ddspd serial pd a0 - a12 a0-a12 : ddr2 sdrams d0 - d15 we we : ddr2 sdrams d0 - d15 cke1 cke : ddr2 sdrams d8 - d15 ba0 - ba1 ba0-ba1 : ddr2 sdrams d0 - d15 odt0 odt : ddr2 sdrams d0 - d7 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d8 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d9 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d10 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d11 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d12 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d13 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d14 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d15 s 1 cke0 cke : ddr2 sdrams d0 - d7 ras ras : ddr2 sdrams d0 - d15 cas cas : ddr2 sdrams d0 - d15 odt1 odt : ddr2 sdrams d8 - d15 m378t6453fg(z)3 / m378t6453fg(z)0
rev. 1.3 aug. 2005 256mb, 512mb unbuffered dimms ddr2 sdram s 0 dqs 0 dqs0 dm0 dm cs dqs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 dqs 1 dqs1 dm1 dm cs dqs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 dqs 2 dqs 2 dm2 dm cs dqs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 dqs 3 dqs3 dm3 dm cs dqs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 dqs 4 dqs4 dm4 dm cs dqs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 dqs 5 dqs5 dm5 dm cs dqs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d5 dqs 6 dqs6 dm6 dm cs dqs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d6 dqs 7 dqs7 dm7 dm cs dqs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d7 notes : 1. dq,dm, dqs/dqs resistors : 22 ohms 5%. 2. bax, ax, ras , cas , we resistors : 3 ohms 5%. functional block diagram: 512mb, 64mx72 ecc module (populated as 2 ranks of x8 ddr2 sdrams) a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp *wire per clock loading table/wiring diagrams * clock wiring clock input ddr2 sdrams *ck0/ ck0 *ck1/ ck1 *ck2/ ck2 6 ddr2 sdrams 6 ddr2 sdrams 6 ddr2 sdrams v ss d0 - d17 v dd /v ddq d0 - d17 d0 - d17 vref v ddspd serial pd a0 - a12 a0-a12 : ddr2 sdrams d0 - d17 we we : ddr2 sdrams d0 - d17 cke1 cke : ddr2 sdrams d9 - d17 ba0 - ba1 ba0-ba1 : ddr2 sdrams d0 - d17 odt0 odt : ddr2 sdrams d0 - d8 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d9 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d10 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d11 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d12 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d13 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d14 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d15 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d16 s 1 cke0 cke : ddr2 sdrams d0 - d8 ras ras : ddr2 sdrams d0 - d17 cas cas : ddr2 sdrams d0 - d17 odt1 odt : ddr2 sdrams d9 - d17 dqs 8 dqs8 dm8 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d8 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d17 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 m391t6453fg(z)3 / m391t6453fg(z)0
rev. 1.3 aug. 2005 256mb, 512mb unbuffered dimms ddr2 sdram absolute maximum dc ratings note : 1. stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stre ss rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this s pecification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. storage temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, plea se refer to jesd51-2 standard. ac & dc operating conditions recommended dc operating conditions (sstl - 1.8) note : there is no specific device v dd supply voltage requirement for sstl-1.8 compliance. however under all conditions v ddq must be less than or equal to v dd . 1. the value of v ref may be selected by the user to provide optimum noise margin in the system. typically the value of v ref is expected to be about 0.5 x v ddq of the transmitting device and v ref is expected to track variations in v ddq . 2. peak to peak ac noise on v ref may not exceed +/-2% v ref (dc). 3. v tt of transmitting device must track v ref of receiving device. 4. ac parameters are measured with v dd , v ddq and v ddl tied together. symbol parameter rating units notes v dd voltage on v dd pin relative to v ss - 1.0 v ~ 2.3 v v 1 v ddq voltage on v ddq pin relative to v ss - 0.5 v ~ 2.3 v v 1 v ddl voltage on v ddl pin relative to v ss - 0.5 v ~ 2.3 v v 1 v in, v out voltage on any pin relative to v ss - 0.5 v ~ 2.3 v v 1 t stg storage temperature -55 to +100 c 1, 2 symbol parameter rating units notes min. typ. max. v dd supply voltage 1.7 1.8 1.9 v v ddl supply voltage for dll 1.7 1.8 1.9 v 4 v ddq supply voltage for output 1.7 1.8 1.9 v 4 v ref input reference voltage 0.49*v ddq 0.50*v ddq 0.51*v ddq mv 1,2 v tt termination voltage v ref -0.04 v ref v ref +0.04 v 3
rev. 1.3 aug. 2005 256mb, 512mb unbuffered dimms ddr2 sdram operating temperature condition note : 1. operating temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, pl ease refer to jesd51.2 standard. 2. at 0 - 85 c, operation temperature range are the temperature which all dram specification will be supported. 3. at 85 - 95 c operation temperature range, doubling refresh commands in frequency to a 32ms period ( trefi=3.9 us ) is required, and to ent er to self refresh mode at this temperature range, an emrs command is required to change internal refresh rate. input dc logic level input ac logic level ac input test conditions notes: 1. input waveform timing is referenced to the input signal crossing through the v ih/il (ac) level applied to the device under test. 2. the input signal minimum slew rate is to be maintained over the range from v ref to v ih (ac) min for rising edges and the range from v ref to v il (ac) max for falling edges as shown in the below figure. 3. ac timings are referenced with input waveforms switching from v il (ac) to v ih (ac) on the positive transitions and v ih (ac) to v il (ac) on the negative transitions. symbol parameter rating units notes toper operating temperature 0 to 95 c 1, 2, 3 symbol parameter min. max. units notes v ih (dc) dc input logic high v ref + 0.125 v ddq + 0.3 v v il (dc) dc input logic low v ddq - 0.3 v ref - 0.125 v symbol parameter ddr2-400, ddr2-533 ddr2-667 units notes min. max. min. max. v ih (ac) ac input logic high v ref + 0.250 - v ref + 0.200 v v il (ac) ac input logic low - v ref - 0.250 v ref - 0.200 v symbol condition value units notes v ref input reference voltage 0.5 * v ddq v1 v swing(max) input signal maximum peak to peak swing 1.0 v 1 slew input signal minimum slew rate 1.0 v/ns 2, 3 v ddq v ih (ac) min v ih (dc) min v ref v il (dc) max v il (ac) max v ss < ac input test signal waveform > v swing(max) delta tr delta tf v ref - v il (ac) max delta tf falling slew = rising slew = v ih (ac) min - v ref delta tr
rev. 1.3 aug. 2005 256mb, 512mb unbuffered dimms ddr2 sdram idd specification parameters definition (idd values are for full operati ng range of voltage and temperature) symbol proposed conditions units notes idd0 operating one bank active-precharge current; t ck = t ck(idd), t rc = t rc(idd), t ras = t rasmin(idd); cke is high, cs\ is high between valid commands; ad- dress bus inputs are switching; data bus inputs are switching ma idd1 operating one bank active-read-precharge current; iout = 0ma; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t rc = t rc (idd), t ras = t rasmin(idd), t rcd = t rcd(idd); cke is high, cs\ is high between valid commands; address bus inputs are switching; data pattern is same as idd4w ma idd2p precharge power-down current; all banks idle; t ck = t ck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating ma idd2q precharge quiet standby current; all banks idle; t ck = t ck(idd); cke is high, cs\ is high; other control and address bus inputs are stable; data bus inputs are floating ma idd2n precharge standby current; all banks idle; t ck = t ck(idd); cke is high, cs\ is high; other control and address bus inputs are switching; data bus inputs are switching ma idd3p active power-down current; all banks open; t ck = t ck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mrs(12) = 0ma ma slow pdn exit mrs(12) = 1ma ma idd3n active standby current; all banks open; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs\ is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching ma idd4w operating burst write current; all banks open, continuous burst writes; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs\ is high between valid commands; address bus inputs are switching; data bus in- puts are switching ma idd4r operating burst read current; all banks open, continuous burst reads, iout = 0ma; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t ras- max(idd), t rp = t rp(idd); cke is high, cs\ is high between valid commands; address bus inputs are switching; data pattern is same as idd4w ma idd5b burst auto refresh current; t ck = t ck(idd); refresh command at every t rfc(idd) interval; cke is high, cs\ is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching ma idd6 self refresh current; ck and ck\ at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating normal ma low power ma idd7 operating bank interleave read current; all bank interleaving reads, iout = 0ma; bl = 4, cl = cl(idd), al = t rcd(idd)-1* t ck(idd); t ck = t ck(idd), t rc = t rc(idd), t rrd = t rrd(idd), t faw = t faw(idd), t rcd = 1* t ck(idd); cke is high, cs\ is high between valid com- mands; address bus inputs are stable during deselects; data pattern is same as idd4r; refer to the following page for detailed timing conditions ma
rev. 1.3 aug. 2005 256mb, 512mb unbuffered dimms ddr2 sdram operating current table(1-1) (t a =0 o c, vdd= 1.9v) m378t3253fg(z)3 / m378t3253fg(z) 0 : 256mb(32mx8 *8) module * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol e6 (ddr2-667@cl=5) d5 (ddr2-533@cl=4) cc (ddr2-400@cl=3) unit notes idd0 840 800 760 ma idd1 920 880 800 ma idd2p 64 64 64 ma idd2q 240 200 200 ma idd2n 280 240 240 ma idd3p-f 280 240 240 ma idd3p-s 120 120 120 ma idd3n 600 560 520 ma idd4w 1,680 1,400 1,080 ma idd4r 1,480 1,280 1,040 ma idd5b 1,360 1,320 1,280 ma idd6 normal 40 40 40 ma idd7 2,120 2,040 2,040 ma m378t6453fg(z)3 / m378t6453fg(z)0 : 512mb(32mx8 *16) module * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol e6 (ddr2-667@cl=5) d5 (ddr2-533@cl=4) cc (ddr2-400@cl=3) unit notes idd0 1,440 1,360 1,280 ma idd1 1,520 1,440 1,320 ma idd2p 128 128 128 ma idd2q 480 400 400 ma idd2n 560 480 480 ma idd3p-f 560 480 480 ma idd3p-s 240 240 240 ma idd3n 1,200 1,120 1,040 ma idd4w 2,280 1,960 1,600 ma idd4r 2,080 1,840 1,560 ma idd5b 1,960 1,880 1,800 ma idd6 normal 80 80 80 ma idd7 2,720 2,600 2,560 ma
rev. 1.3 aug. 2005 256mb, 512mb unbuffered dimms ddr2 sdram operating current table(1-2) (t a =0 o c, vdd= 1.9v) m391t3253fg(z)3 / m391t3253fg(z)0 : 256mb(32mx8 *9) ecc module * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol e6 (ddr2-667@cl=5) d5 (ddr2-533@cl=4) cc (ddr2-400@cl=3) unit notes idd0 945 900 855 ma idd1 1,035 990 900 ma idd2p 72 72 72 ma idd2q 270 225 225 ma idd2n 315 270 270 ma idd3p-f 315 270 270 ma idd3p-s 135 135 135 ma idd3n 675 630 585 ma idd4w 1,890 1,575 1,215 ma idd4r 1,665 1,440 1,170 ma idd5b 1,530 1,485 1,440 ma idd6 normal 45 45 45 ma idd7 2,385 2,295 2,295 ma m391t6453fg(z)3 / m391t6453fg(z)0 : 512mb(32mx8 *18) ecc module * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol e6 (ddr2-667@cl=5) d5 (ddr2-533@cl=4) cc (ddr2-400@cl=3) unit notes idd0 1,620 1,530 1,440 ma idd1 1,710 1,620 1,485 ma idd2p 144 144 144 ma idd2q 540 450 450 ma idd2n 630 540 540 ma idd3p-f 630 540 540 ma idd3p-s 270 270 270 ma idd3n 1,350 1,260 1,170 ma idd4w 2,565 2,205 1,800 ma idd4r 2,340 2,070 1,755 ma idd5b 2,205 2,115 2,025 ma idd6 normal 90 90 90 ma idd7 3,060 2,925 2,880 ma
rev. 1.3 aug. 2005 256mb, 512mb unbuffered dimms ddr2 sdram input/output capacitance (v dd =1.8v, v ddq =1.8v, t a =25 o c) * dm is internally loaded to match dq and dqs identically. parameter symbol min max min max units non-ecc m378t3253fg(z)3 m378t3253fg(z)0 m378t6453fg(z)3 m378t6453fg(z)0 input capacitance, ck and ck cck0 - 24 - 26 pf cck1 - 25 - 28 cck2 - 25 - 28 input capacitance, cke and cs ci 1 - 42 - 42 input capacitance, addr,ras ,cas ,we ci 2 - 42 - 42 input/output capacitance, dq, dm, dqs, dqs cio - 6 - 10 ecc symbol m391t3253fg(z)3 m391t3253fg(z)0 m391t6453fg(z)3 m391t6453fg(z)0 units input capacitance, ck and ck cck0 - 25 - 28 pf cck1 - 25 - 28 cck2 - 25 - 28 input capacitance, cke and cs ci 1 - 44 - 44 input capacitance, addr,ras ,cas ,we ci 2 - 44 - 44 input/output capacitance, dq, dm, dqs, dqs cio - 6 - 10
rev. 1.3 aug. 2005 256mb, 512mb unbuffered dimms ddr2 sdram electrical characteristics & ac timing for ddr2-667/533/400 sdram (0 c < t case < 95 c; v ddq = 1.8v + 0.1v; v dd = 1.8v + 0.1v) refresh parameters by device density speed bins and cl, trcd, trp, trc and tras for corresponding bin timing parameters by speed grade (refer to notes for informations re lated to this table at the bottom) parameter symbol 256mb 512mb 1gb 2gb 4gb units refresh to active/refresh command time trfc 75 105 127.5 195 tbd ns average periodic refresh interval trefi 0 c t case 85 c 7.8 7.8 7.8 7.8 7.8 s 85 c < t case 95 c 3.9 3.9 3.9 3.9 3.9 s speed ddr2-667(e6) ddr2-533(d5) ddr2-400(cc) units bin (cl - trcd - trp) 5 - 5- 5 4 - 4 - 4 3 - 3 - 3 parameter min max min max min max tck, cl=3 5 8 5 8 5 8 ns tck, cl=4 3.75 8 3.75 8 5 8 ns tck, cl=5 3 8 - - - - ns trcd 15 15 15 ns trp 15 15 15 ns trc 54 55 55 ns tras 39 70000 40 70000 40 70000 ns parameter symbol ddr2-667 ddr2-533 ddr2-400 units notes min max min max min max dq output access time from ck/ck tac -450 +450 -500 +500 -600 +600 ps dqs output access time from ck/ck tdqsck -400 +400 -450 +450 -500 +500 ps ck high-level width tch 0.45 0.55 0.45 0.55 0.45 0.55 tck ck low-level width tcl 0.45 0.55 0.45 0.55 0.45 0.55 tck ck half period thp min(tcl, tch) x min(tcl, tch) x min(tcl, tch) x ps 20,21 clock cycle time, cl=x tck 3000 8000 3750 8000 5000 8000 ps 24 dq and dm input hold time tdh 175 x 225 x275x ps 15,16,17 dq and dm input setup time tds 50 x 100 x150 x ps 15,16,17 control & address input pulse width for each input tipw 0.6 x 0.6 x0.6x tck dq and dm input pulse width for each input tdipw 0.35 x 0.35 x0.35 x tck data-out high-impedance time from ck/ck thz x tac max x tac max x tac max ps dqs low-impedance time from ck/ck tlz(dqs) tac min tac max tac min tac max tac min tac max ps 27 dq low-impedance time from ck/ck tlz(dq) 2*tac min tac max 2* tacmin tac max 2* tacmin tac max ps 27 dqs-dq skew for dqs and associated dq signals tdqsq x 250 x 300 x 350 ps 22 dq hold skew factor tqhs x 350 x 400 x 450 ps 21 dq/dqs output hold time from dqs tqh thp - tqhs x thp - tqhs x thp - tqhs x ps write command to first dqs latching transition tdqss wl-0.25 wl+0.25 wl-0.25 wl+0.25 wl-0.25 wl+0.25 tck dqs input high pulse width tdqsh 0.35 x 0.35 x 0.35 x tck
rev. 1.3 aug. 2005 256mb, 512mb unbuffered dimms ddr2 sdram parameter symbol ddr2-667 ddr2-533 ddr2-400 units notes min max min max min max dqs input low pulse width tdqsl 0.35 x 0.35 x 0.35 x tck dqs falling edge to ck setup time tdss 0.2 x 0.2 x 0.2 x tck dqs falling edge hold time from ck tdsh 0.2 x 0.2 x 0.2 x tck mode register se t command cycle time tmrd 2 x 2 x 2 x tck write postamble twpst 0.4 0.6 0.4 0.6 0.4 0.6 tck 19 write preamble twpre 0.35 x 0.35 x 0.35 x tck address and control input hold time tih 275 x375 x 475 x ps 14,16,18 address and control input setup time tis 200 x250 x 350 x ps 14,16,18 read preamble trpre 0.9 1.1 0.9 1.1 0.9 1.1 tck 28 read postamble trpst 0.4 0.6 0.4 0.6 0.4 0.6 tck 28 active to active command period for 1kb page size products trrd 7.5 x7.5 x 7.5 x ns 12 active to active command period for 2kb page size products trrd 10 x10 x 10 x ns 12 four activate window for 1kb page size products tfaw 37.5 37.5 37.5 ns four activate window for 2kb page size products tfaw 50 50 50 ns cas to cas command delay tccd 2 2 2 tck write recovery time twr 15 x15 x 15 x ns auto precharge write recovery + precharge time tdal twr+trp x twr+trp x twr+trp x tck 23 internal write to read command delay twtr 7.5 x7.5 x10 x ns internal read to precharge command delay trtp 7.5 7.5 7.5 ns 11 exit self refresh to a non-read command txsnr trfc + 10 trfc + 10 trfc + 10 ns exit self refresh to a read command txsrd 200 200 200 tck exit precharge power down to any non-read command txp 2 x 2 x 2 x tck exit active power down to read command txard 2 x 2 x 2 x tck 9 exit active power down to read command (slow exit, lower power) txards 6 - al 6 - al 6 - al tck 9, 10 cke minimum pulse width (high and low pulse width) tcke 3 33tck odt turn-on delay taond222222tck odt turn-on taon tac(min) tac(max)+ 0.7 tac(min) tac(max)+ 1 tac(min) tac(max)+ 1 ns 13, 25 odt turn-on(power-down mode) taonpd tac(min)+ 2 2tck+tac( max)+1 tac(min)+ 2 2tck+tac( max)+1 tac(min)+ 2 2tck+tac (max)+1 ns odt turn-off delay taofd 2.5 2.5 2.5 2.5 2.5 2.5 tck odt turn-off taof tac(min) tac(max)+ 0.6 tac(min) tac(max)+ 0.6 tac(min) tac(max)+ 0.6 ns 26 odt turn-off (power-down mode) taofpd tac(min)+ 2 2.5tck+ta c(max)+1 tac(min)+ 2 2.5tck+ tac(max)+ 1 tac(min)+ 2 2.5tck+ tac(max)+ 1 ns odt to power down entry latency tanpd 3 3 3 tck odt power down exit latency taxpd 8 8 8 tck ocd drive mode output delay toit 0 12 0 12 0 12 ns minimum time clocks remains on after cke asynchronously drops low tdelay tis+tck +tih tis+tck +tih tis+tck +tih ns 24
rev. 1.3 aug. 2005 256mb, 512mb unbuffered dimms ddr2 sdram physical dimensions: 32mbx8 based 32mx64 /x72 module(1 rank) 131.35 units : millimeters 133.35 10.00 1.270 0.10 2.7 spd n/a (for x72) 128.95 (2) 2.50 (2x)4.00 30.00 2.30 17.80 (for x64) ecc the used device is 32m x8 ddr2 sdram, fbga. ddr2 sdram part no : k4t56083qf m378t3253fg(z)3 / m391t3253fg(z)3 a b 63.00 55.00 2.50 1.00 0.20 2.500.20 detail b 5.00 detail a 4.00 1.500.10 0.800.05 4.00 3.80 3.00 4.00 m378t3253fg(z)0 / m391t3253fg(z)0
rev. 1.3 aug. 2005 256mb, 512mb unbuffered dimms ddr2 sdram 2.50 physical dimensions: 32mbx8 based 64mx64 /x72 module(2 ranks) 131.35 units : millimeters 133.35 10.00 1.270 0.10 4.00 128.95 (2) 2.50 (2x)4.00 2.30 17.80 n/a (for x64) (for x72) ecc the used device is 32m x8 ddr2 sdram, fbga. ddr2 sdram part no : k4t56083qf spd m378t6453fg(z)3 / m391t6453fg(z)3 1.00 0.20 2.500.20 detail b 5.00 detail a 4.00 1.500.10 0.800.05 4.00 3.80 3.00 4.00 a b 63.00 55.00 30.00 n/a (for x72) (for x64) ecc m378t6453fg(z)0 / m391t6453fg(z)0
rev. 1.3 aug. 2005 256mb, 512mb unbuffered dimms ddr2 sdram revision history revision 1.0 (jan. 2004) - initial release revision 1.1 (jun. 2004) - added lead-free part number in the ordering information - changed idd2p revision 1.2 (jan. 2005) - revised tih value of 667 speed revision 1.3 (aug. 2005) - added dummy pad pcb product part number in ordering information

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